1. Field of the Invention
The present invention relates to semiconductor device fabrication and more particularly, to low resistance barrier layers for reliably isolating, adhering, and passivating copper metal and achieving the optimum cubic crystalline texture in the copper metal.
2. Description of Related Art
Advances in materials technology are playing an important role in improving semiconductor device performance and the reduction of power consumption in solid state electronic components and systems. Conventional semiconductor technologies, e.g., 0.50 xcexcm CMOS, typically use multilevel aluminum alloy metallizations and chemical-vapor-deposited (CVD) tungsten plugs. The tungsten plug process is being replaced by the use of aluminum plugs in the device interconnect contacts and via holes.
Aluminum plugs reduce process complexity, increase manufacturing yield, and decrease interconnect resistance. Although the overall interconnect resistance is being reduced, the power losses in on-chip interconnect structures remains significant in integrated circuits, particularly as device density increases. To reduce such power losses further, the metallization structures need to be made with materials that have resistivities lower than aluminum and other related new materials technologies such as low-k interlevel dielectrics.
Because of its lower bulk and skin resistance, an effective replacement for aluminum is copper that is isolated from the electrically active devices by a reliable barrier material. Methods to deposit copper metallizations include electroless deposition, metal organic chemical vapor deposition (MOCVD), electroplating, and collimated physical vapor deposition (c-PVD). Regardless of the way copper is deposited, the metal must be isolated or encapsulated so that it will not diffuse into the surrounding areas of the device and thus degrade performance.
Copper appears to be the best of the available choices from the list of known low resistivity metals, e.g., silver, aluminum, gold, copper, and tungsten. Copper offers many advantages: low resistivity, ease of deposition, high thermal conductivity, a lower temperature coefficient of resistance than aluminum and tungsten, a lower coefficient of thermal expansion than aluminum, the highest melting point except for tungsten, and the lowest adiabatic temperature rise due to Joule heating. Copper is also expected to offer lower electromigration (by several orders of magnitude) in poly or single crystalline materials. The copper texture also enhances performance, yielding lower stresses and other beneficial properties.
The shrinking feature sizes of ULSI circuits places severe requirements on interconnect metallization technologies, particularly where severe topography exists, such as in submicron diameter contact windows and vias. Since sub-0.25 xcexcm feature size integrated circuits will be performance limited by the resistance in the metal interconnects, copper metallization is better than aluminum because of copper""s lower resistivity and higher resistance to electromigration.
Given these advantages, semiconductor manufacturers are expending significant efforts to incorporate copper into upper-level metallizations. The use of copper, however, also requires the incorporation of diffusion barriers, adhesion promoters, and passivation layers. Diffusion barriers that are thermally stable, chemically stable, and electrically conductive are needed to isolate copper due to its high atomic mobility. Copper diffuses rapidly in silicon and dielectrics, which strongly degrades semiconductor device performance, and thus materials must be identified that block this diffusion.
Adhesion promoters are needed since copper does not xe2x80x9cwetxe2x80x9d or bond well to silicon dioxide and other dielectric surfaces, especially when subjected to thermal cycling. Passivation layers are required to prevent environmental degradation of the etched or chemically/mechanically polished copper surfaces. Substantial efforts have been made to identify barrier layer materials that meet all major requirements, e.g., diffusion barrier, adhesion promoter, passivation barrier, and low electrical resistivity for a low contact/via resistance.
Tantalum, TiN, TiCON, and TiOS have been used for barrier layer materials. Other conventional barrier technologies include amorphous refractory alloys. These diffusion barrier materials have been shown to be effective at very high temperatures. While all of these materials can inhibit the movement of copper, none of them optimize the microstructure of the copper as it is deposited. Thus, the potential for significant enhancements in the performance of the metallization are lost. Barrier materials that produce copper with a very uniform microstructure that includes a strong (100) cubic texture and a large grain size are desirable.
It is the object of the present invention to address the problems inherent in the conventional barrier systems and provide a low resistance barrier material that effectively isolates, adheres to, and passivates copper metal for semiconductor fabrication.
The present invention is a low resistivity refractory metal carbide barrier system that reliably isolates, adheres, and passivates copper surfaces in semiconductor fabrication. This copper metallization barrier layer controls and optimizes the texture and grain size (i.e., microstructure) of copper metallizations and thereby maximizes the performance and reliability of the metallization and overall semiconductor device. Suitable metal carbide barrier layer materials include carbides of transition metals, such as chromium carbide (Cr3C2), vanadium carbide (VC), niobium carbide (NbC), tantalum carbide (TaC), tungsten carbide (WC), and molybdenum carbide (MoC). These materials have either a cubic (NaCl) structure at equilibrium (e.g., VC, NbC, TaC) or a metastable cubic structure (e.g., Cr3C2, MoC, WC) that is formed under non-equilibrium conditions.
These metal carbides are insoluble or have limited solubility in copper in the solid and liquid states (depending on the specific carbide) and are effective diffusion barriers, i.e., these carbides can block copper diffusion and isolate copper metallizations from the rest of an integrated circuit device. Furthermore, these metal carbides are wetted by copper, which is critical to providing excellent adhesion between copper and materials such as silicon or conventional dielectrics.
One embodiment of the present invention is a multilayer film of metal carbide barrier layers and copper layers, where the metal carbide layers afford microstructural control of the copper layers. For example, one or more barrier layers of chrome carbide (Cr3C2) are deposited on the substrate (e.g., silicon, silicon dioxide) in conjunction with copper metallizations. The thickness of the carbide layers may be as thin as 200 xc3x85 or less. The final, terminating layer of copper of the Cu/Cr3C2 multilayer may be, and typically is, thicker than the underlying copper layers. The copper and the carbide barrier materials can be deposited by a variety of processes, such as MOCVD, electroless deposition, collimated physical vapor deposition (c-PVD), magnetron sputtering, and electroplating.
The present invention provides a robust, production-worthy, integrated deposition technology for low power, high performance, high reliability copper metallizations with critical dimensions of 0.25 xcexcm and less. The cubic barrier layer or layers enhance and maintain the (100) crystallographic texture and orientation of the copper metallizations, as well as increase strength, passivation, and thermal stability. The barrier layer also isolates the copper from contamination associated with subsequent processing. Other objects and advantages of the present invention will become apparent from the following description and accompanying drawing.